Why does compilation fail during the Logic Generation Stage with the F-Tile SDI II Intel® FPGA IP in TX and RX simplex mode and when placed in the same channel with the Intel Agilex® 7 device?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, the F-Tile SDI II Intel® FPGA IP will fail during compilation process when merging both TX and RX simplex mode in the same channel, the following error messages will appear during the Logic Generation stage:

• Error (21842): Support logic cannot be generated because IP components used in the design have conflicting settings
• Error: Design cannot be programmed onto available F-Tiles because given location constraints are conflicting, or because the design requires more resources compared to what is available on current device
• Error: Quartus Prime Logic Generation Tool was unsuccessful. 22 errors, 0 warnings
• Error (21794): Quartus Prime Full Compilation was unsuccessful. 24 errors, 2 warnings

This problem is due to the Intel® Quartus® Prime Pro Edition Software being unable to merge the single SDI II TX profile with multiple profiles of the SDI II RX when in multirate mode.

To work around this problem when using TX and RX in simplex mode, the TX and RX lanes must be seperated into two different channels to pass compilation at the Logic Generation stage.

This problem has been fixed in the Intel® Quartus® Prime Pro Edition Software 22.2 version.