Article ID: 000089948 Content Type: Troubleshooting Last Reviewed: 03/20/2023

Should I preserve the unused transmitter pins of an E-Tile Channel PLL on the Intel® Stratix® 10 or the Intel Agilex® 7 E-Tile FPGAs?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Stratix® 10 E-Tile Transceiver Native PHY
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    No, you do not need to preserve the unused transmitter pins of an E-Tile Channel PLL on the Intel® Stratix® 10 or the Intel Agilex® 7 E-Tile FPGAs.

    Example: If your current design implements an E-Tile Channel PLL in location 4 that clocks E-Tile channels 0-3 in External EMIB Clocking mode, you do not need to preserve the TX pins of channel 4 if that channel were later to be used as a data channel instead of a Channel PLL.

     

     

     

    Resolution

    This information will be added to a future revision of the E-Tile Transceiver PHY User Guide.

    Related Products

    This article applies to 4 products

    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
    Intel® Stratix® 10 DX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA

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