Why is '256-bit' the only option available for the 'Application Interface Width' parameter of the L-tile and H-tile Avalon® Memory mapped Intel® FPGA IP for PCI Express*

Starting with the Intel® Quartus® Prime Pro Edition Software version 21.4, the '64-bit' option for the 'Application Interface Width' parameter of the L-tile and H-tile Avalon® Memory mapped Intel® FPGA IP for PCI Express* is no longer available.

To migrate an L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* instance from a '64-bit' 'Application Interface Width' configuration to a '256-bit' 'Application Interface Width' configuration.

• Open the Platform Designer system where the L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* is instantiated.
• Under the 'System Settings' tab make the following changes:
  • Set the 'Application Interface Width' parameter to '256-bit'.
  • Set the 'Hard IP Mode' parameter to the same configuration but using a '256-bit' interface.
• Under the 'Avalon-MM Settings' tab  make the following changes:
  • Set the 'Avalon-MM address width' to '64-bit'.
  • If the 'Enable non-bursting Avalon-MM Slave interface with individual byte access (TXS)' parameter is set to 'ON', adjust the 'Address width of accessible PCIe memory space (TXS)' to accommodate the new address range of the system.
• Go to the 'System' menu and select the 'Assign Base Address' option. Platform Designer will rearrange the system address map to accommodate the changes.
• Save the Platform Designer system.
• Regenerate the Platform Designer system.