Why does my design containing the F-Tile JESD204C Intel® FPGA IP using Intel Agilex® 7 fail to pass the Intel® Quartus® “Support Logic Generation” phase?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software versions 21.3 and 21.4, designs containing the F-Tile JESD204C Intel® FPGA IP using Intel Agilex® 7 devices will fail to pass the Intel® Quartus® Prime Pro Edition Software “Support Logic Generation” phase.

This error is encountered when the selected data rate is not divisible by 64.

To work around this problem, choose a data rate in the JESD204C IP which is divisible by 64.

If this is not practical, then you must select a System PLL output frequency using the following equation:
System PLL output frequency = (Data rate/32) * 2

The resultant System PLL output frequency must be less than or equal to 1 GHz per the System PLL specification.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.