Article ID: 000088803 Content Type: Product Information & Documentation Last Reviewed: 03/28/2023

Why do the out_refclk_fgt and out_system_pll_clk ports of the F-Tile Reference and System PLL Clocks Intel® FPGA IP fail to toggle when simulating the Intel Agilex® 7 F-Tile FPGA PHY IPs?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The out_refclk_fgt and out_system_pll_clk ports of the F-Tile Reference and System PLL Clocks Intel® FPGA IP will not toggle in the simulation waveform. However, Intel Agilex® 7 F-Tile FPGA PHY IPs are still functional in simulation.

    Resolution

    There is currently no plan to fix this problem.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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