Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3, you may see this internal error when compiling designs that target Intel Agilex® 7 devices and includes any External Memory Interfaces Intel Agilex® 7 FPGA IP.
The error occurs when the assigned pin-outs of the device are invalid due to non-contiguous EMIF sub-banks being used for the location assignments.
To avoid this error, correct the pin assignments to create a valid device pin-out for the External Memory Interfaces Intel Agilex® 7 FPGA IP.
Refer to the External Memory Interfaces Intel Agilex® FPGA IP User Guide: Intel Agilex FPGA EMIF IP Pin and Resource Planning for creating valid pin assignments for the design.
Additionally, you may find the following documents to be helpful: Agilex EMIF Pin Planner Tool and Agilex EMIF Pin Information Document.
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4.