Article ID: 000087343 Content Type: Troubleshooting Last Reviewed: 05/10/2017

Is there a known issue in the Quartus Prime software with Analog-to-Digital Converter (ADC) I/O rule checking in MAX 10 devices?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Modular ADC core Intel® FPGA IP
  • Modular Dual ADC core Intel® FPGA IP
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    Description

    Yes, due to an issue in Quartus® Prime software versions 16.1.2 and earlier, the fitter does not perform the Analog-to-Digital Converter (ADC) I/O Restriction physical rule based checking in MAX® 10 devices. 

    These rules define the number of General Purpose I/Os (GPIO) allowed in a particular bank based on the I/O's drive strength, when using ADCs in the design. These rules are based on noise calculation to analyze accurately the impact of I/O placement on the ADC performance.

    Workaround

    This issue is fixed in Quartus Prime software version 17.0 

     

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

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