Description
You might encounter this error in the Intel® Quartus® Prime Pro Edition Software release version 17.1 and earlier when compiling Intel® Stratix® 10 FPGA designs that contain pin location assignments to transceiver related pins where there are no transceivers physically connected to these pins in your design.
Resolution
To avoid this error, either connect these pins to transceiver instances in your design or remove the pin location assignments.
This problem is scheduled to be resolved in a future release of the Intel Quartus Prime Pro Edition Software.