Article ID: 000087147 Content Type: Troubleshooting Last Reviewed: 02/08/2012

Stratix V Hard IP for PCI Express Root Port Includes Unsupported Interrupt Signals

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The top-level HDL file for the Stratix V Hard IP for PCI Express Root Port includes the following unsupported signals: aer_msi_num, pex_msi_num, app_msi_req, app_msi_ack, app_msi_tc[2:0], and app_msi_num[4:0]. However, these signals are not available for Root Ports.

    Resolution

    This issue is fixed in version 11.1 SP2 of the Stratix V Hard IP for PCI Express IP core.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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