You might see this error when using the PLL Intel® FPGA IP with Stratix® V, Arria® V, and Cyclone® V devices and specifying phase shifts for multiple output clocks. The IP might show this error if one or more phase shift settings are not achievable. However, it may also list Actual Phase Shift settings that are also invalid.
To get phase shift settings as close as possible to what you desire for multiple output clock frequencies, use the Physical Output Enable option and manually enter the M and N counter values to achieve a VCO frequency that allows you to achieve your required output frequencies as well as a suitable phase step resolution.