Due to the large operating temperature range of the A10 SoC device (from -40C to 100C for Industrial grade) and the extensive range of available NAND flash devices, you may need to relax the NAND timing settings to achieve maximum operational stability for your system.
A patch is available to fix this problem for SoC EDS 16.0. This patch configures the nand_config register to add additional timing delay for NAND timings Twp, Trp, Tclse, Tcleh, Tcesu, Tceh, Talesu, Taleh, and Tdh.
Download the patch using the link below, then follow the steps below:
1. Apply the patch to the u-boot-socfpga directory in your Arria 10 BSP using git apply: cd <bsp name>/u-boot-socfpga; git apply <patch name>.patch
2. Re-generate the BSP: make clean; make
Note: This patch is not included in the later release of u-boot-socfpga