Article ID: 000086820 Content Type: Troubleshooting Last Reviewed: 06/06/2023

Why is readdatavalid not asserted in Intel Agilex® EMIF Intel® FPGA IP Memory-Mapped Configuration and Status Register (MMR) Interface?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2 and earlier, when Intel Agilex® EMIF Intel® FPGA IP Memory-Mapped Configuration and Status Register (MMR) Interface is enabled, you might see that read data is available but readdatavalid signal is not asserted in MMR interface.

    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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