Article ID: 000086802 Content Type: Product Information & Documentation Last Reviewed: 03/17/2023

How can the data stored in the read data FIFO in Intel® Stratix® 10 Serial Flash Mailbox Client Intel® FPGA IP core be read with a JTAG host?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Mailbox Client Intel® Stratix® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The read data FIFO can be accessed through the “rd_mem” bus in the Intel® Stratix® 10 Serial Flash Mailbox Client Intel® FPGA IP core. To read the data stored in the read data FIFO, you need to read data from the “rd_mem” bus. Refer to the IP rd_mem’s base and end address  in the Platform Designer for the start address and list of addresses that you can read into.

    For more details about the read operation flow, refer to Stratix® 10 Serial Flash Mailbox Client Intel® FPGA IP Core User Guide.

     

    Resolution

    For more details about the read operation flow, refer to Stratix® 10 Serial Flash Mailbox Client Intel® FPGA IP Core User Guide.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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