Due to the limitation of the PHY Lite for Parallel Interfaces Intel® FPGA IP, you may see the error message above if you have more than one PHY Lite for Parallel Interfaces Intel FPGA IP place in the same I/O bank.
To work around this problem, avoid placing more than one PHY Lite for Parallel Interfaces Intel® FPGA IP place in the same I/O bank. This is because each of the PHY Lite for Parallel Interfaces Intel FPGA IP has a specific interface requirement which required a specific PLL setting. However, there is only one PLL available in a given bank.