Why does reconfiguration of Intel® Stratix® 10 MX devices fail when the hbm_only_reset_in port of High Bandwidth Memory (HBM2) Interface Intel® FPGA IP is connected to the output of Intel® FPGA Reset Release FPGA IP or other core logic?

When using Intel® Quartus® Prime Pro Edition Software version 21.1 and earlier, performing reconfiguration of Intel® Stratix® 10 MX devices in user mode will fail if the hbm_only_reset_in port for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP is connected to the output of Intel® FPGA Reset Release FPGA IP or other core logic.

During reconfiguration, if the hbm_only_reset_in is driven with logic value 1'b1, then the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP will always be in reset state and result in configuration failure.

To work around this problem, download and install patch 0.24fw for the Intel® Quartus® Prime Pro Edition Software version 21.1 from the appropriate link below.

• Download version 21.1 Patch 0.24fw for Windows (.exe)
• Download version 21.1 Patch 0.24fw for Linux (.run)
• Download the Readme for the Intel® Quartus® Prime Pro Edition software version 21.1 Patch 0.24fw (.txt)

You may reuse an existing SOF file to generate the .jic or .rpd file after the patch is installed. 

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.2.