Error (10198): Verilog HDL error at phylite_io_bufs.sv(1078): part-select direction is opposite from prefix index direction

Due to a problem in the Quartus® Prime Software version 18.1 and earlier, you may see similar errors as shown below when the Arria® 10 PHYLite IP is configured as a 48-bit output interface with the Use Output Strobe option disabled.

In the Quartus Prime Standard Edition Software,

    Error (10198): Verilog HDL error at phylite_io_bufs.sv(1078): part-select direction is opposite from prefix index direction

    Error (12152): Can't elaborate user hierarchy "ed_synth_altera_phylite_180_7qlz52a:phylite_0_example_design|ed_synth_altera_phylite_arch_nf_180_wqpiemi:core|phylite_core_20:arch_inst|phylite_io_bufs:u_phylite_io_bufs"

In the Quartus Prime Pro Edition Software,

    Error (13437): Verilog HDL error at ed_synth_phylite_0_example_design__phylite_io_bufs.sv(1195): part-select direction is opposite from prefix index direction 

    Error (13224): Verilog HDL or VHDL error at ed_synth_phylite_0_example_design__phylite_io_bufs.sv(1195): index 48 is out of range [47:0] for 'group_data_out_n'

To work around these errors, the Arria® 10 PHYLite IP can be configured as a 47-bit or smaller data width interface.

This problem will be fixed in a future release of the Quartus® Prime Software.