Article ID: 000086544 Content Type: Troubleshooting Last Reviewed: 01/04/2023

What is the state of HPS GPIO on Intel® Cyclone® V SoC and Arria® V SoC devices during cold reset?

Environment

  • Intel® Quartus® Prime Pro Edition
  • GPIO Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Hard Processor System(HPS) GPIO on Intel® Cyclone® V SoC and Arria® V SoC devices are in the default state during cold reset. The default state of I/O’s on the HPS GPIO Controller/Module is input. HPS I/O is configured as GPIO when the HPS user pin mapping is applied by the Pre-loader.  

    Resolution

    This information has been added to the 20.1 release of the Intel® Cyclone® V/Arria® V Hard Processor System Technical Reference Manual.

    Related Products

    This article applies to 5 products

    Cyclone® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SE SoC FPGA
    Arria® V SX SoC FPGA
    Arria® V ST SoC FPGA

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