Article ID: 000086538 Content Type: Troubleshooting Last Reviewed: 08/21/2023

Why does the Intel® Stratix® 10 Hard Processor System encounter an error while accessing the Secure Device Manager QSPI when the configuration clock source is set to the OSC_CLK_1 pin?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the U-Boot bootloader code, the Intel® Stratix® 10 Hard Processor System may report an error similar to the following when attempting to access the Secure Device Manager QSPI flash memory and the configuration clock source is set to the OSC_CLK_1 pin:

     

    SOCFPGA_STRATIX10 # sf probe

    SF: Calibration failed (low range)

    SF: unrecognized JEDEC id bytes: ff, fc, 82

    Failed to initialize SPI flash at 0:0 (error -2)

    Resolution

    To avoid this problem, set the configuration clock source to use the Internal Oscillator.  

     

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 SX SoC FPGA