Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 17.1 Update 1 and earlier, you might see this internal error during placement of a Intel® Stratix® 10 FPGA design containing multiple clock domains.
The internal error might occur when a design contains multiple asynchronous clock domains, which have not been declared as being asynchronous in the Synopsys Design Constraints files (.sdc).
To work around this problem, ensure that all asynchronous clock domains are declared as being asynchronous using the set_clock_groups command.
For example:
set_clock_groups -asynchronous -group [get_clocks <clock A>] -group [get_clocks <clock B>]
This problem is scheduled to be resolved in a future release of the Intel Quartus Prime Pro Edition Software.