Article ID: 000086334 Content Type: Troubleshooting Last Reviewed: 06/30/2017

Why does my Stratix IV scfifo and dcfifo output register get cleared during the assertion of sclr during functional simulation?

Environment

  • Intel® Quartus® Prime Standard Edition
  • FIFO Intel® FPGA IP
  • Simulation, Debug and Verification
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Stratix® IV scfifo and dcfifo simulation model the output register will be incorrectly cleared during the assertion of the sclr input.


    Resolution

    In hardware and gate level simulation the output register will retain its previous value.

    This problem is scheduled to be fixed in a future release of the Quartus Prime Standard Edition software.

    Related Products

    This article applies to 1 products

    Stratix® IV FPGAs

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