How do I decode the AXI ID fields from the HPS-FPGA bridges for Cyclone® V and Arria® V SoC devices?

The ARID, AWID, WID, RID, and BID signals indicate the master and routing for a particular memory access that is made by the HPS-FPGA bridges (either the HPS-to_FPGA bridge or the Lightweight HPS-to-FPGA bridge).

For Arria® V and Cyclone® V SoC devices, the AXI ID that is outputted from the L3 interconnect is a 12-bit vector made up of these fields:
ID[12]: Interconnect ID, IID
ID[11:3]: Virtual ID, VID
ID[2:0]: Slave Interconnect ID, SIID

The VID is received from the master which the transaction is received from, and the IID and SIID are assigned by the L3 interconnect as shown:

The 8-bit VID is set by the master that sent the transaction to the L3 interconnect.

The VID for the MPU master is set according to the AMBA® Level 2 cache controller L2C-310 revision r3p0 Technical Reference Manual, available from the ARM® info center website http://infocenter.arm.com.

The VID for the FPGA2HPS master is from the 8-bit AXI ID inputs to the FPGA2HPS bridge.

The VID for the DMA master has bits 7:4 set to 0, and bits 3:0 set according to the ARM CoreLink DMA-330 revision r1p1 Technical Reference Manual.

The VID for the EMAC0 and EMAC1 masters is set to 8h00 for Rx DMA accesses and 8h01 for Tx DMA accesses.

The VID is always set to 0 for USB0, USB1, TMC, DAP, NAND, and SDMMC masters.

This information is included starting with version 16.1 of the respective device handbooks.