In the Intel® FPGA SDK for OpenCL™ 17.0 BSP flow, some clocks may show timing failures in the BSP during an import compile even though the base seed met timing. This is a false failure and shows up as some of the constraints from the base compile gets ignored due to the order at which SDC constraints gets applied during the import compile.
Users will need to comment out or remove the following lines in their top.qsf file:
# base revision compile SDC constraints only
set_global_assignment -name SDC_FILE base.sdc
set_global_assignment -disable -name SDC_FILE top.sdc
set_global_assignment -disable -name SDC_FILE top_post.sdc
It will be required to do another import compile after changing the QSF file
aoc --board <BSP_name> <kernel_name>.cl
This problem is scheduled to be fixed in a future release of the Intel® FPGA SDK for OpenCL™.