Description
Every PLL has a minimum input frequency limit and maximum input frequency limit that it can achieve lock given the configured parameters. These are listed in the Quartus® II Compilation Report - Fitter - Resource Section - PLL Summary. The Freq min lock and Freq max lock values show the dynamic range of the PLL input clock. The output clock(s) will track the input clock according to the PLL counter settings. Changing the input frequency may cause the PLL to lose lock, but as long as the input clock remains within the minimum and maximum frequency specifications, the PLL will be able to achieve lock.
Environment
PLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT