Critical Warning Message for Stratix V Devices

When you compile a design that contains an LVDS SERDES megafunction and targets a Stratix V device, the Quartus II software displays a warning message similar to the following:

Critical Warning: DIVCLK port on the PLL is not properly connected on instance altera_tse_pcs_pma:altera_tse_pcs_pma_inst|altera_tse_pma_lvds_rx:the_altera_tse_pma_lvds_rx|altlvds_rx:ALTLVDS_RX_component|lvds_rx_ofs3:auto_generated|pll_sclk~PLL_OUTPUT_COUNTER. The output clock port on the PLL must be connected.

This issue affects all Stratix V designs that contain LVDS SERDES megafunction.

No workaround.This issue will be fixed in a future version of the Triple-Speed Ethernet MegaCore function.