Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.1, you might see this error when running a post-fit or post-synthesis gate-level VHDL (.vho) simulation that includes high-speed transceivers.
To work around this problem, edit the .vho file to ensure that the following library and package declarations are in place.
For Intel® Stratix® 10 devices
LIBRARY FOURTEENNM;
LIBRARY FOURTEENNM_HSSI_ALL;
LIBRARY IEEE;
USE FOURTEENNM.FOURTEENNM_COMPONENTS.ALL;
USE FOURTEENNM_HSSI_ALL.CT1_HSSI_COMPONENTS.ALL;
USE FOURTEENNM_HSSI_ALL.CTP_HSSI_COMPONENTS.ALL;
USE FOURTEENNM_HSSI_ALL.CT1_HIP_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
For Intel Agilex® devices
LIBRARY TENNM;
LIBRARY TENNM_HSSI_ALL;
LIBRARY IEEE;
USE TENNM.TENNM_COMPONENTS.ALL;
USE TENNM_HSSI_ALL.CT1_HSSI_COMPONENTS.ALL;
USE TENNM_HSSI_ALL.CTP_HSSI_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
The above changes address the problem for the ModelSim* Intel® FPGA Edition simulator.
For all other simulators, run the Intel® Quartus® Prime Software library compiler to generate and optionally run the library compilation commands compatible with the modifed .vho file.
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.2.