Issue 338064: Volume 1, Chapter 8 SEU Mitigation for Cyclone® V Devices, Version 2015.06.12
In page 8-9, Timing section states as follows:
The CRC_ERROR pin is always driven low during CRC calculation for a minimum of 32 clock cycles. When an error occurs, the pin is driven high once the EMR is updated or 32 clock cycles have lapsed, whichever comes last. Therefore, you can start retrieving the contents of the EMR at the rising edge of the CRC_ERROR pin. The pin stays high until the current frame is read and then driven low again for a minimum of 32 clock cycles.
But this is incorrect. It should state as follows:
The CRC_ERROR pin is always driven low during CRC calculation. When an error occurs, the EDCRC hard block takes 32 clock cycles to update the EMR, the pin is driven high once the EMR is updated. Therefore, you can start retrieving the contents of the EMR at the rising edge of the CRC_ERROR pin. The pin stays high until the current frame is read and then driven low again for 32 clock cycles.
Figure 8-6 states CRC Calculation (minimum 32 clock cycles), but it should state CRC Calculation (32 clock cycles).
Issue 132933: Volume1 Chapter 8, SEU Mitigation for Cyclone V Devices, version 2014.06.30
Table 8-3 incorrectly shows Cyclone E in the variant column. It should show Cyclone V E.
Issue 136679: I/O Features in Cyclone V Devices, Version 2013.06.21
Page 33 states the weak pull-up resistor is not supported on dedicated clock pins. This is incorrect, the weak pull-up resistor is supported on dedicated clock pins.
Issue 138112: Cyclone V Device Datasheet, Version 1.3 2012.12.28
Table 5-24 shows the programmable IOE features and settings for Cyclone V devices. The pre-emphasis feature row indicates the assignments apply to allow values- 0 (enabled) and 1(disabled). This cell should be updated to 0(disable) and 1(enable).
Issue 156380: Clock Networks and PLLs in Cyclone V Devices, Version 2013.05.06
There are two bullets for requirements when using automatic clock switchover, the first one is incorrect. It says:
"Both clock inputs must be running."
The purpose of automatic clock switchover is to switch between clocks if one stops running. The actual requirement is both clocks need to be running when the FPGA is configured. The bullet should say:
"Both clock inputs must be running when the FPGA is configured."
Issue 140192: I/O Features in Cyclone V Devices: Version 2013.6.21
Table 5-10 indicates the 3.3V input signal is not supported when VCCIO=2.5V in MuliVolt I/O Support. The table is incorrect and the 2.5V VCCIO can support a 3.3V input signal.
Issue 138311: Cyclone V Device Datasheet: Version 3.4
Table 51 shows the value for tCO would be a maximum of 4us but this is incorrect, the maximum value for tCO should be 4ns.
Issue 110591: Cyclone V Device Overview: Version 2012.12.28
Page 14, Figure 7 shows a M385 pin package is available, this is a typo and will be updated to a M386 pin package.
Issue 98650: Volume 1, Chapter 4, Clock Networks and PLLs in Cyclone V Devices, Version 2012.12.28
The handbook currently states that External Feedback mode is supported on all Cyclone V PLLs, except on the corner fractional PLLs. This is incorrect. The handbook should state that External Feedback mode is supported on all Cyclone V PLLs, except on the strip fractional PLLs.
Issue 92790: Volume 1, Chapter 5, I/O Features in Cyclone V Devices, Version 2012.12.28
Table 5-15: Modular I/O Banks for Cyclone V E A7 F672 package should have the following I/O counts:
Bank 6A = 48 I/O pins available
Bank 5B = 32 I/O pins available
Issue 92829: Volume 1, Chapter 5, I/O Features in Cyclone V Devices, Version 2012.12.28
Table 5-23 should indicate that Current Strength 16, 8, 4 mA are available for 3.3V LVTTL I/O standards. Only 8, 4 mA is supported in HPS.
Resolved Issues:
Issue 67593: Volume 1, Chapter 5, I/O Features in Cyclone V Devices, Version 2.0
Statements implying VREF pins are available as user I/O pins removed in version 2012.12.28, VREF pins do not have user I/O pin functionality.
Issue 41653: Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices, version 1.1
Configuration Schemes for Cyclone V Devices for AS (x1, x4) modes update to show AS configuration supports only 3.0 and 3.3V.
Issue 41653: Device Interfaces and Integration Basics for Cyclone V Devices, version 1.1
This chapter has been integrated to the device handbook, volume 1. Active serial configuration has been updated to show support only for 3.0 and 3.3V VCCPGM, 1.8V is not supported.
Issue 30381: Volume 2, Chapter 5, I/O Features in Cyclone V Devices, Version 1.1
Table 5-3 updated to show the 3.3-V LVCMOS I/O standard supports only a 2mA current strength.