Article ID: 000085643 Content Type: Troubleshooting Last Reviewed: 03/31/2023

Why doesn't tx_par_err[1] assert with bad parity of Tx avalon-st packet on my simulation?

Environment

  • Quartus® II Subscription Edition
  • PCI Express
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to problems in the Intel® Quartus® II software version 12.0sp2 and earlier, the simulation model of PCIe HIP does not assert tx_par_err[1] with bad parity of Tx avalon-st packet even though tx_par_err[0]is asserted with the parity and packet.

    Resolution

    This issue is fixed in Intel® Quartus® software version 13.1.

    Related Products

    This article applies to 1 products

    Stratix® V GX FPGA

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