Description
This error may occur when you generate a Verilog netlist for Primetime, when the TimeQuest Timing Analyzer is enabled in the Quartus® II software version 6.1.
This error occurs when your design has assignments that trigger hierarchical synthesis (such as one global synthesis assignment, and the same assignment with a different value on an entity), which causes the Primetime EDA Netlist Writer to generate a hierarchical netlist.
This problem is fixed beginning with the Quartus II software version 7.0.
You can also use mySupport to request patch 0.24 for the Quartus II software version 6.1 which fixes the problem.