Due to a problem in the Quartus® II software version 14.0 Intel® Arria® 10 FPGA Edition, you might see small hold violations. These occur because of the fast routing of the Intel Arria 10 device.
To work around this problem, overconstrain the hold requirement during the fitting of your design by adding the following constraints to your Synopsys Design Constraints (.SDC) file:
set quartus_exe $::TimeQuestInfo(nameofexecutable)
if { $quartus_exe == "quartus_fit" } {
post_message -type info “Over constraining hold”
set_clock_uncertainty 0.20 –add –hold –enable_same_physical_edge \
-from [get_clocks {clk}] –to [get_clocks {clk}]
}
This gives the fitter a tighter requirement while still using the correct hold requirement for sign-off timing.
This constraint should only be added when needed rather than globally and can also be applied to specific paths rather than whole clock domains. If this does not fix your hold violations, larger values can overconstrain the violating paths.