Why does the Gen3 x8 AVMM 256-bit DMA design hang when the host attempts to perform two accesses in a row to the descriptor controller interface?

In Quartus® II software version 13.1, you may see the Hard IP for PCI Express® using Avalon® Memory-Mapped interface with DMA design crash if the descriptor controller interface is accessed using a burst transaction.

This is due to the Avalon-MM Descriptor Controller only supporting single cycle access.

If an Avalon-MM Master component performs two sequential accesses, or a burst transaction to the descriptor controller, then the Qsys interconnect component may generate a burst cycle from two single cycles.

In Quartus® II version 13.1 Hard IP for PCIe Avalon-MM with DMA designs ensure that only single cycle accesses are made to the DMA descriptor controller interface.

This issue will be fixed in a future version of the Quartus® II software.