clock0 and clock1.
The VCO's floor frequency limit can extend below 200 MHz depending on process, voltage, and temperature. Therefore, the VCO's floor frequency limit can vary fromlot-to-lot. While Altera specifies a minimum VCO frequency, the output frequency of the clock cannot be guaranteed if the input clock has been removed.
When the input clock is disabled, the PLL will lose lock and the LOCK pin will go low. Once an input clock is re-applied, the PLL will re-lock onto the clock signal and the lock period time must be allowed to ensure the PLL has regained lock.
During simulation in the Altera® Quartus® II software, the PLL clock output(s) will be low because the simulator cannot model the frequency drift. The LOCK pin will also be low at this time. Once the input clock is re-applied again, the PLL clock output(s) will begin to toggle in simulation.