Description
The mapping between the input clock pins, PLL counter outputs, and clock control block inputs is as follows for Stratix® III and Stratix IV devices:
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inclk[0] and inclk[1]—can be fed by any of the four dedicated clock pins on the same side of the device
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inclk[2]—can be fed by PLL counters C0 and C2 from the two center PLLs on the same side of the device
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inclk[3]—can be fed by PLL counters C1 and C3 from the two center PLLs on the same side of the device
For dynamic selection of these clock sources, you can use the ALTCLKCTRL megafunction in your design.
The corner PLLs (L1, L4, R1, and R4) and the corresponding clock input pins (PLL_L1_CLK and so forth) do not support dynamic selection for the GCLK network.
The clock source selection for the GCLK and RCLK networks from the corner PLLs (L1, L4, R1, and R4) and the corresponding clock input pins (PLL_L1_CLK and so forth) is controlled statically using configuration bit settings in the configuration file (.sof or .pof) generated by the Quartus® II software.