Article ID: 000085328 Content Type: Error Messages Last Reviewed: 09/11/2012

Internal Error: Sub-system: FTITAN, File: /quartus/fitter/ftitan/ftitan_expert.cpp, Line: 4418 Final postfit netlist check failed

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see this internal error when compiling designs with Quartus® II software versions 10.0 SP1 and earlier. You may also see the following message
Error: The lvds clock and the DPA clock frequency of SERDES receiver atom "rx_0" must be the same.

These errors are the result of an LVDS receiver with an incorrectly configured DPA clock.

To correctly use the DPA function of the LVDS receiver, in the ALTPLL megafunction associated with the LVDS receiver you should enable the Use these clock settings for the DPA clock (For the Left-Right PLL type only) option on the Output Clocks page of the ALTPLL MegaWizard™ Plug-In. This option is disabled and cannot be selected when running the Quartus II software versions 10.0 SP1 and earlier and targeting an Arria® II GX device.

A patch is available to fix this problem for the Quartus II software version 10.0 SP1. Download and install Patch 1.119 from the appropriate link below. This patch enables the option for the DPA clock setting in the ALTPLL MegaWizard.

This problem is scheduled to be fixed in a future release of the Quartus II software.

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