Article ID: 000085319 Content Type: Troubleshooting Last Reviewed: 01/01/2015

Do Arria V devices have similar I/O placement restrictions with HSTL and SSTL pins as compared to Arrix II GX devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No, Arria® V devices do not have similar I/O placement restrictions with HSTL and SSTL pins as compared to Arrix II GX devices.

You may utilize all available HSTL and SSTL output/bidirectional pins in an Arria V device I/O bank.

For the I/O placement restrictions for Arria II GX devices, you can refer to the Arria II Device Family Pin Connection Guidelines (PDF).

Related articles

Related Products

This article applies to 8 products

Arria® V GT FPGA
Stratix® V E FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Stratix® V GX FPGA
Arria® V SX SoC FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.