A signal output's slew rates vary significantly based on load conditions. Altera's input/output buffer information specification (IBIS) models provide the necessary information to determine how the board's transmission line effects will require slowing the slew rate.
Table 1 shows slew rates measured for both rising and falling edges under the following conditions:
- From 10 to 90% of the output voltage swing
- Under a 35-pF non-terminated load
- Room temperature
- Nominal VCC
Table 1. MAX 7000AE and 3000A Slew Rates | ||
VCCIO (V) | Normal Slew Rate (V/ns) | Slow Slew Rate (V/ns) |
---|---|---|
3.3 | 1.3 | 1.2 |
2.5 | 1 | 0.9 |
Note: The effect of slew rate control becomes more dramatic when more outputs are switching. As such, the slew rate control has a significant effect on reducing ground bounce and VCC sag effects of adjacent switching signals.
The slow slew rate logic synthesis option can be turned on and off globally in the MAX PLUS® II software using the following steps:
- Choose Global Project Logic Synthesis (Assign menu).
- Select Define Synthesis Style (Global Project Logic Synthesis box).
- Turn Slow Slew Rate on or off.
- Choose OK twice.