Article ID: 000085227 Content Type: Troubleshooting Last Reviewed: 08/03/2023

Why can I assign more than a 32-bit data width to the Arria® V Hard Memory Controller?

Environment

  • Quartus® II Software
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Although the Arria® V handbook states that the A1, A3, A5, and A7 devices can support up to a 32-bit width controller on top or bottom edges, the Quartus® II software incorrectly allows you to implement a 40-bit controller without an error message.

     

    Resolution

    Please follow the document to set the data width up to 32 bits. 

    Related Products

    This article applies to 5 products

    Arria® V GT FPGA
    Arria® V GZ FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Arria® V GX FPGA

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.