Article ID: 000085221 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does the DDR/DDR2 High Performance (HP) controller enable CKE signals for many more clock cycles than required, when in power down mode after issuing an auto-refresh command?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

In Quartus® II and IP version 8.0 and later there is an issue which keeps the CKE enabled for tRFC time.

This behavior will be corrected in the future Quartus II and IP version.

Related Products

This article applies to 9 products

Cyclone® III FPGAs
Arria® GX FPGA
HardCopy™ III ASIC Devices
Stratix® II GX FPGA
Stratix® II FPGAs
Stratix® IV GX FPGA
Stratix® III FPGAs
Arria® II GX FPGA
Stratix® IV E FPGA

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