Description
You may be seeing the red "error" LED illuminating and the "CFG_DONE" led not illuminating on the Stratix® III FPGA Development Kit when trying to use Design Security feature because when using Design Security there is a different MSEL0 pin setting. For this particular board there is jumper J13 for MSEL0 that will need to be left open so that MSEL0 can be pulled to VCC. Since the configuration scheme for this board when using Design Security will be Fast Passive Parallel (FPP) using a MAX® II device and a 512MB flash you will need an MSEL[2:0] pin setting of 001. If not using Design Security then the MSEL[2:0] pins will be set to 000.
Environment
BUILT IN - ARTICLE INTRO SECOND COMPONENT