Article ID: 000085150 Content Type: Error Messages Last Reviewed: 08/27/2013

Error: enable0 input port of SERDES receiver or transmitter atom "rx_0" must be driven by a clock output port of the fast PLL

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The ALTLVDS_RX megafunction in the Quartus® II software version 10.0 SP1 incorrectly sets the rx_enable pin to std_logic_vector(0 downto 0) in External PLL mode. The corrrect syntax should be std_logic. 

    Resolution

    A patch is available to fix this problem for the Quartus II software version 10.0 SP1. Download and install Patch 1.114 from the appropriate link below.

    This issue is fixed in the Quartus II Software version 10.1.

    Related Products

    This article applies to 4 products

    Stratix® IV E FPGA
    Stratix® IV GX FPGA
    Stratix® IV GT FPGA
    Stratix® III FPGAs

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