IP Compiler for PCI Express Cannot Negotiate to Gen 2 Data Rate on Some Devices

Auto negotiation to the Gen 2 data rate may fail in some devices. When this failure occurs, the IP Compiler for PCI Express is unable to switch to the Gen 2 data rate.

All IP Compiler for PCI Express Gen 2 variations that target an Arria II GZ, Stratix IV GT, or Stratix IV GX device.

No workaround exists for variations with transceivers configured to use the ATX PLL. You must configure the transceivers to use the CMU PLL.

To enable the IP core to negotiate to the Gen 2 data rate, generate a configuration that uses the CMU PLL. In versions 10.0 and 10.1, but not in version 11.0 or 11.1, you must then follow these steps:

1. After you generate the PCI Express compiler variations and before you compile the project, change directory to the location of the transceiver megafunction instance. The directory contains a <variation>_serdes.v or <variation>_serdes.vhd file, depending on the HDL.
2. Depending on the transceiver megafunction instance HDL, follow one of these steps:
3. If your transceiver megafunction instance is generated in Verilog HDL, type the following command:

• If your transceiver megafunction instance is generated in VHDL, type the following command:

This issue will be fixed in a future version of the IP Compiler for PCI Express.