Why are the thermal resistance for junction to ambient specifications different in the Stratix® II handbook, volume 2 chapter 10 when compared to the specifications in the Stratix II Early Power Estimator?

Description The thermal resistance for junction to ambient (._JA) specifications shown in the Stratix II handbook are based on the device properties when simulated using the JEDEC board standard which defines the board properties such as stack up and copper density. The ._JA specifications shown in the Stratix II Early Power Estimator are based on the device properties when simulated using an Altera custom board which resembles a typical size and stack up for the device package. The Altera custom board model has these properties: PCB is 2.5mm thick for all cases.

Package	Signal Layers	Power/GND Layers	Dimensions (mm)
F1508	12	12	100 x 100
F1020	10	10	93 x 93
F780	9	9	89 x 89
F672	8	8	87 x 87
F484	7	7	83 x 83

 Notes to table:
1. Power layer copper (Cu) thickness 35m, Cu 90%
2. Signal layer copper (Cu) thickness 17m, Cu 15%