Article ID: 000084855 Content Type: Troubleshooting Last Reviewed: 04/18/2023

Can I safely ignore DIV_CLK critical warnings for the fPLL when used in the 66:40 gearbox ratio on Stratix® V GX/GS/GT FPGA and Arria® V GZ FPGA transceivers?

Environment

  • Quartus® II Software
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    If you instantiate multiple copies of the same transceiver instance using the 66:40 gearbox, the Quartus® II software will merge the multiple fPLLs into a single entity if possible. When this is done, the Quartus II software will report this critical warning on the fPLLs that have been removed from the design.

    Resolution

    Yes, you can safely ignore DIV_CLK critical warnings reported for the fPLL used in the 66:40 gearbox ratio on Stratix® V GX/GS/GT FPGA and Arria® V GZ FPGA transceivers.

    Related Products

    This article applies to 3 products

    Stratix® V GX FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA

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