Article ID: 000084818 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I have to disable the DM pins generation in the DDR3 SDRAM High Performance Controller or Altmemphy IP Megawizard when implementing DDR3 SDRAM controller in x4 mode in Stratix III or Stratix IV devices?

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Description You have to disable the DM pins generation in the DDR3 SDRAM High Performance Controller or Altmemphy IP Megawizard when implementing DDR3 SDRAM controller in x4 mode in Stratix® III or Stratix IV devices because there are not enough pins in a x4 DQS group to include the DM pin.

Related Products

This article applies to 4 products

Stratix® III FPGAs
Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA

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