Article ID: 000084790 Content Type: Product Information & Documentation Last Reviewed: 12/17/2015

How do I reduce the percentage of crosstalk and SSN towards differential pins in Cyclone V devices?

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Description

The attached document will describe how to reduce the percentage (%) of crosstalk and percentage (%) of Simultaneous Switching Noise (SSN) towards differential pins in the Quartus® II software when targeting Cyclone® V devices.

 

Resolution

 

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This article applies to 6 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Cyclone® V ST SoC FPGA
Cyclone® V E FPGA
Cyclone® V SE SoC FPGA

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