Description
A bug in the IP version 7.2SP3 and earlier resulted in the Differential DQS Mode registers not being correctly set during DDR2 memory initialization.
Hence the DDR2 memory was only using single-ended DQS mode signalling, whilst the Stratix® III device was configured for Differential Mode.
This will degrade both read and write timing.
DDR SDRAM is NOT affected as only Single Ended is supported.
DDR3 SDRAM is NOT affected, as only Differential mode is supported.
Stratix II Series and earlier devices are not affected as differential DQS mode was not supported.
This bug is fixed in version 8.0 of Quartus® II software and the IP.
Users must upgrade and regenerate their Stratix III DDR2 IP if Differential DQS mode is required.