Article ID: 000084764 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Are there any changes to the Fast PLL (FPLL) compensation value in Quartus® II version 4.0 SP1 when using the FPLL in the Stratix® EP1S40 device?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description Yes, the Quartus® II software versions 4.0 and earlier were over-compensating for the Regional Clock network delays by 400ps when using the corner FPLLs and by 1.99ns when using the side FPLLs to drive the RCLK network. Quartus II Version 4.0 SP1 fixes this bug. Customers using FPLLs to drive the GCLK network will not see this over-compensation when using Quartus II ver 3.0 SP1 and later.

Related Products

This article applies to 1 products

Stratix® FPGAs

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.