Description
You may get a Cyclone® device LVDSCLKn Boundary-Scan Failure becasue at power up, CLK1& CLK3 are disabled while CLK0 & CLK2 are enabled. If CLK1 or CLK3 needs to be verified in a boundary scan testing, the input buffer of the clock pins can be enabled by configuring them using CONFIG_IO instruction.
This can be done by applying the CONFIG_IO instruction after power-up before carrying out pre-configuration boundary scan testing. Refer to MorphIO: An I/O Reconfiguration Solution for Altera Devices (PDF) for more information on the CONFIG_IO instruction.
This can be done by applying the CONFIG_IO instruction after power-up before carrying out pre-configuration boundary scan testing. Refer to MorphIO: An I/O Reconfiguration Solution for Altera Devices (PDF) for more information on the CONFIG_IO instruction.
If you intend to test these CLK pins in pre-configuration boundary scan testing, download the modified Cyclone 1149.1 Boundary-Scan Description Language (BSDL) Files.
If these CLK pins do not need to be in the JTAG chain for boundary scan testing, use the latest Cyclone 1149.1 BSDL files.