Article ID: 000084633 Content Type: Troubleshooting Last Reviewed: 12/31/2013

Why doesn't pulsing transceiver edge sensitive input signals have an effect in Cyclone V, Arria V and Stratix V transceiver devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When driving the Cyclone® V, Arria® V and Stratix® V device transceiver edge sensitive signals, such as the rx_std_wa_patternalign signal, you must still comply with the minimum pulse width requirement. The minimum typical pulse width is two parallel clock cycles.

Resolution

 

Related Products

This article applies to 8 products

Arria® V GX FPGA
Arria® V SX SoC FPGA
Cyclone® V SX SoC FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA

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