Article ID: 000084534 Content Type: Troubleshooting Last Reviewed: 09/02/2021

Why is the SOPC Builder system generation only successful for the first attempt but fails for the successive attempts in Quartus II? When it fails, the SOPC Builder hangs during the system generation at "Info: : No Extra Settings:"

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

This issue occurs if you have instantiated UniPHY-based memory interface IP cores such as DDR2 and DDR3 SDRAM Controller with UniPHY, QDR II and QDR II SRAM Controller with UniPHY and RLDRAM II Controller with UniPHY in SOPC Builder, Quartus® II software version 10.0 or 10.0 SP1.

 

Temporary workaround to this issue is to delete the rtl folder located in all UniPHY source folders in Quartus II software project directory each time you re-generate the SOPC Builder.

 

This issue is fixed in Quartus II version 10.1.

 

 

Resolution

This issue is fixed in Quartus II version 10.1.

Related Products

This article applies to 4 products

Stratix® IV GT FPGA
Stratix® IV E FPGA
Stratix® IV GX FPGA
Stratix® III FPGAs