This issue occurs if you have instantiated UniPHY-based memory interface IP cores such as DDR2 and DDR3 SDRAM Controller with UniPHY, QDR II and QDR II SRAM Controller with UniPHY and RLDRAM II Controller with UniPHY in SOPC Builder, Quartus® II software version 10.0 or 10.0 SP1.
Temporary workaround to this issue is to delete the rtl folder located in all UniPHY source folders in Quartus II software project directory each time you re-generate the SOPC Builder.
This issue is fixed in Quartus II version 10.1.
This issue is fixed in Quartus II version 10.1.