Article ID: 000084488 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Is the JTAG TRST pin level triggered or edge triggered?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description The optional JTAG TRST input pin is IEEE 1149 compliant, therefore this pin will be edge triggered.

Related Products

This article applies to 4 products

Arria® FPGAs
Stratix® FPGAs
Cyclone® FPGAs
Mercury™